Altera Transceiver PHY IP Core User Manual
Page 34
Name
Value
Description
PCS / PMA interface width
32
40
For Stratix V and Arria V GZ devices only:
Specifies the data interface width between the 10G
PCS and the transceiver PMA. Smaller width
corresponds to lower PCS latency but higher
frequency.
• For 40 bit width, rx_recovered_clock is 257.8125
MHz and the gearbox ratio is 66:40.
• For 40 bit width, rx_recovered_clock is
322.265626 MHz and the gearbox ratio is 66:32.
32 bit PCS / PMA interface with does not support
data rates up to 10.3125 Gbps in C4/I4 Arria V GZ
device variants. Refer to Arria V GZ Device
Datasheet for details on data rates supported by
different device variants.
Additional Options
Enable additional control and
status pins
On/Off
If you turn this option On, the following 2 signals
are brought out to the top level of the IP core to
facilitate debugging: rx_hi_ber and rx_block_lock.
Enable rx_recovered_clk pin
On/Off
When you turn this option On, the RX recovered
clock signal is an output signal.
Enable pll_locked status port
On/Off
For Arria V and Stratix V devices:
When you turn this option On, a PLL locked status
signal is included as a top-level signal of the core.
Use external PMA control and
reconfig
On/Off
For Stratix IV devices:
If you turn this option on, the PMA controller and
reconfiguration block are external, rather than
included in the 10GBASE-R PHY IP Core, allowing
you to use the same PMA controller and reconfigu‐
ration IP cores for other protocols in the same
transceiver quad.
When you turn this option On, the
cal_blk_
powerdown
(0x021) and
pma_tx_pll_is_locked
(0x022) registers are available.
Enable rx_coreclkin port
On/Off
When selected,
rx_coreclkin
is sourced from the
156.25 MHz
xgmii_rx_clk
signal avoiding the use
of a FPLL to generate this clock. This clock drives
the read side of RX FIFO.
3-10
General Option Parameters
UG-01080
2015.01.19
Altera Corporation
10GBASE-R PHY IP Core