Altera Transceiver PHY IP Core User Manual
Page 82
Signal Name
Direction
Description
ref_clk_1g
input. The random error without a rate
match FIFO mode is:
• +/- 1 ns at 1000 Mbps
• +/- 5 ns at 100 Mbps
• +/- 25 ns at 10 Mbps
rx_sync_status
Output
When asserted, indicates the Standard PCS word
aligner has aligned to in incoming word alignment
pattern.
tx_pcfifo_error_1g
Output
When asserted, indicates that the Standard PCS TX
phase compensation FIFO is full.
rx_pcfifo_error_1g
Output
When asserted, indicates that the Standard PCS RX
phase compensation FIFO is full.
lcl_rf
Input
When asserted, indicates a Remote Fault (RF).The
MAC to sends this fault signal to its link partner.
Remote Fault (RF) is encoded in bit D13 of the base
Link Codeword. Bit 3 of the
Auto Negotiation
Advanced Remote Fault
register (0xC2) records
this error.
tm_in_trigger[3:0]
Input
This is an optional signal that can be used for
hardware testing by using an oscilloscope or logic
analyzer to trigger events. If unused, tie this signal
to 1'b0.
tm_out_trigger[3:0]
Output
This is an optional signal that can be used for
hardware testing by using an oscilloscope or logic
analyzer to trigger events. You can ignore this signal
if not used.
rx_rlv
Output
When asserted, indicates a run length violation.
rx_clkslip
Input
When you turn this signal on, the deserializer skips
one serial bit or the serial clock is paused for one
cycle to achieve word alignment. As a result, the
period of the parallel clock can be extended by 1
unit interval (UI). This is an optional control input
signal.
rx_latency_adj_1g[21:0]
Output
When you enable 1588, this signal outputs the real
time latency in GMII clock cycles (125 MHz) for the
RX PCS and PMA datapath for 1G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits
10 to 21 represent the number of clock cycles.
tx_latency_adj_1g[21:0]
Output
When you enable 1588, this signal outputs real time
latency in GMII clock cycles (125 MHz) for the TX
PCS and PMA datapath for 1G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits
10 to 21 represent the number of clock cycles.
4-26
10GBASE-KR PHY Control and Status Interfaces
UG-01080
2015.01.19
Altera Corporation
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option