Altera Transceiver PHY IP Core - Manual (Page 160)

Word Addr Bits R/W Register Name Description
0x022 [31:0] R
pma_tx_pll_is_locked
Bit[P] indicates that the TX CMU PLL (P) is
locked to the input reference clock. There is
typically one
pma_tx_pll_is_locked
bit per
system. This register is not available for
Arria V, Arria V GZ, Cyclone V, or Stratix V
devices.
Reset Control Registers–Automatic Reset Controller
0x041 [31:0] RW
reset_ch_bitmask Bit mask for reset registers at addresses
0x042 and 0x044. The default value is all 1s.
Channel <
n
> can be reset when
bit<
n
> = 1.
0x042 [1:0]
W
reset_control
(write) Writing a 1 to bit 0 initiates a TX digital
reset using the reset controller module. The
reset affects channels enabled in the
reset_
ch_bitmask
. Writing a 1 to bit 1 initiates a
RX digital reset of channels enabled in the
reset_ch_bitmask
. This bit self-clears.
R
reset_status
(read) Reading bit 0 returns the status of the reset
controller TX ready bit. Reading bit 1
returns the status of the reset controller RX
ready bit. This bit self-clears.
Reset Controls –Manual Mode
0x044
[31:4,0] RW Reserved It is safe to write 0s to reserved bits.
[1] RW
reset_tx_digital
Writing a 1 causes the internal TX digital
reset signal to be asserted, resetting all
channels enabled in
reset_ch_bitmask
.
You must write a 0 to clear the reset
condition.
[2] RW
reset_rx_analog
Writing a 1 causes the internal RX analog
reset signal to be asserted, resetting the RX
analog logic of all channels enabled in
reset_ch_bitmask
. You must write a 0 to
clear the reset condition.
[3] RW
reset_rx_digital
Writing a 1 causes the RX digital reset signal
to be asserted, resetting the RX digital
channels enabled in
reset_ch_bitmask
.
You must write a 0 to clear the reset
condition.
PMA Control and Status Registers
6-20 XAUI PHY Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation XAUI PHY IP Core
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