Altera Transceiver PHY IP Core User Manual
Page 200
Signal Name
Direction
Description
pipe_rx_data_valid
Output
For Gen3, this signal is deasserted by the PHY to instruct
the MAC to ignore
pipe_rxdata
for one clock cycle. A
value of 1 indicates the MAC should use the data. A
value of 0 indicates the MAC should not use the data.
pipe_rxvalid[
Output
Asserted when RX data and control are valid.
pipe_rxelecidle
Output
When asserted, indicates receiver detection of an
electrical idle.
For Gen2 and Gen3 data rates, the MAC uses logic to
detect electrical idle entry instead of relying of this
signal.
rxstatus
Output
This signal encodes receive status and error codes for the
receive data stream and receiver detection.The following
encodings are defined:
• 3’b000–receive data OK
• 3’b001–1 SKP added
• 3’b010–1 SKP removed
• 3’b011–Receiver detected
• 3’b100–Both 8B/10B or 128b/130b decode error and
(optionally) RX disparity error
• 3’b101–Elastic buffer overflow
• 3’b110–Elastic buffer underflow
• 3’b111–Receive disparity error, not used if disparity
error is reported using 3’b100.
pipe_phystatus
Output
This signal is used to communicate completion of
several PHY requests.
Figure 8-4: Rate Switch from Gen1 to Gen2 Timing Diagram
In the figure, Time T1 is pending characterization and <n> is the number of lanes.
pipe_pclk
pipe_rate[1:0]
0
1
0
2
T1
T1
T1
62.5 MHz (Gen1)
62.5 MHz (Gen1)
250 MHz (Gen3)
125 MHz (Gen2)
pipe_phystatus[<
n>-1:0]
Related Information
8-12
PHY for PCIe (PIPE) Output Data to the PHY MAC
UG-01080
2015.01.19
Altera Corporation
PHY IP Core for PCI Express (PIPE)