Altera Transceiver PHY IP Core User Manual
Page 697
Date
Document
Version
Changes Made
May 2011
1.2
• Added details about the 0 ready latency for
tx_ready
.
• Added PLL support to lane rate parameter description in
Interlaken PHY General Options.
• Moved dynamic reconfiguration for the transceiver outside of
the Interlaken PHY IP Core. The reconfiguration signals now
connect to a separate Reconfiguration Controller IP Core.
• Added a reference to PHY IP Design Flow with Interlaken for
Stratix V Devices which is a reference design that implements the
Interlaken protocol in a Stratix V device.
• Changed supported metaframe lengths from 1–8191 to 5–8191.
• Added
pll_locked
output port.
• Added
indirect_addr
register at 0x080 for use in accessing
PCS control and status registers.
• Added new Bonded group size parameter.
PHY IP Core for PCI Express PHY (PIPE)
May 2011
1.2
• Renamed to PHY IP Core for PCI Express.
• Moved dynamic reconfiguration for the transceiver outside of
the PHY IP Core. The reconfiguration signals now connect to a
separate Reconfiguration Controller IP Core.
• Removed ×2 support.
Custom PHY Transceiver
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-37
Additional Information for the Transceiver PHY IP Core
Altera Corporation