Sdr xgmii rx interface, Transceiver serial data interface, Xaui phy clocks, reset, and powerdown interfaces – Altera Transceiver PHY IP Core User Manual
Page 153: Sdr xgmii rx interface -13, Transceiver serial data interface -13
Table 6-7: SDR TX XGMII Interface
Signal Name
Direction
Description
xgmii_tx_dc[71:0]
Output
Contains 4 lanes of data and control for XGMII. Each lane
consists of 16 bits of data and 2 bits of control.
• Lane 0–[7:0]/[8], [43:36]/[44]
• Lane 1–[16:9]/[17], [52:45]/[53]
• Lane 2–[25:18]/[26], [61:54]/[62]
• Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_tx_clk
Input
The XGMII SDR TX clock which runs at 156.25 MHz or
312.5 for the DDR variant.
SDR XGMII RX Interface
This section describes the signals in the SDR RX XGMII interface.
Table 6-8: SDR RX XGMII Interface
Signal Name
Direction
Description
xgmii_rx_dc_[71:0]
Input
Contains 4 lanes of data and control for XGMII. Each lane
consists of 16 bits of data and 2 bits of control.
• Lane 0–[7:0]/[8], [43:36]/[44]
• Lane 1–[16:9]/[17], [52:45]/[53]
• Lane 2–[25:18]/[26], [61:54]/[62]
• Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_rx_clk
Output
The XGMII SDR RX clock which runs at 156.25 MHz.
Transceiver Serial Data Interface
This section describes the signals in the XAUI transceiver serial data interface.
The XAUI transceiver serial data interface has four lanes of serial data for both the TX and RX interfaces.
This interface runs at 3.125 GHz or 6.25 GHz depending on the variant you choose. There is no separate
clock signal because it is encoded in the data.
Table 6-9: Serial Data Interface
Signal Name
Direction
Description
xaui_rx_serial_data[3:0]
Input
Serial input data.
xaui_tx_serial_data[3:0]
Output
Serial output data.
XAUI PHY Clocks, Reset, and Powerdown Interfaces
This section describes the clocks, reset, and oowerdown interfaces.
UG-01080
2015.01.19
SDR XGMII RX Interface
6-13
XAUI PHY IP Core
Altera Corporation