Altera Transceiver PHY IP Core - Manual (Page 177)

Signal Name Direction Description
pll_locked
Output In multilane Interlaken designs, this signal is the
bitwise
AND
of the individual lane
pll_locked
signals.
This output is synchronous to the
phy_mgmt_clk
clock domain.
tx_sync_done
Output
When asserted, indicates that all
tx_parallel_data
lanes are synchronized and ready for valid user data
traffic. The Interlaken MAC must wait for this signal
to be asserted before initiating valid user data transfers
on any lane. This output is synchronous to the
tx_
coreclkin
clock domain. For consistent
tx_sync_
done
performance, Altera recommends using
tx_
coreclkin
and
rx_coreclkin
frequency of lane (data
rate/40).
You must invoke a hard reset using
mgmt_rst_reset
and
phy_mgmt_clk_reset
to initiate the synchroniza‐
tion sequence on the TX lanes.
After
tx_sync_done
is asserted, you must never allow
the TX FIFO to underflow, doing so requires you to
hard reset to the Interlaken PHY IP Core.
For Quartus versions prior to 12.0, you must pre-fill
the TX FIFO before
tx_sync_done
can be asserted.
Use the following Verilog HDL assignment for
Quartus II releases prior to 12.0:
assign tx_parallel_data[65] = (!tx_sync_
done)?1'b1:tx_datain_bp[0];
Interlaken PHY Avalon-ST RX Interface
This section lists the signals in the Avalon-ST RX interface.
Table 7-5: Avalon-ST RX Signals
Signal Name Direction Description
rx_parallel_data<n>
[63:0]
Output Avalon-ST data bus driven from the RX PCS to the FPGA
fabric. This output is synchronous to the
rx_coreclkin
clock
domain.
7-10 Interlaken PHY Avalon-ST RX Interface
UG-01080
2015.01.19
Altera Corporation Interlaken PHY IP Core
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