Altera Transceiver PHY IP Core - Manual (Page 184)

Table 7-10: Interlaken PHY Registers
Word Addr Bits R/W Register Name Description
PMA Common Control and Status Registers
0x022 [
-1:0] RO
pma_tx_pll_is_locked
If <
p
> is the PLL number, Bit[<
p
>]
indicates that the TX CMU PLL (<
p
>) is
locked to the input reference clock.
There is typically one
pma_tx_pll_is_
locked
bit per system.
Reset Control Registers-Automatic Reset Controller
0x041 [31:0] RW
reset_ch_bitmask Reset controller channel bitmask for
digital resets. The default value is all 1s.
Channel can be reset when bit<
n
> =
1. Channel <
n
> cannot be reset when
bit<
n
> = 0.
The Interlaken PHY IP requires the use
of the embedded reset controller to
initiate the correct the reset sequence. A
hard reset to
phy_mgmt_clk_reset
and
mgmt_rst_reset
is required for
Interlaken PHY IP.
Altera does not recommend use of a soft
reset or the use of these reset register bits
for Interlaken PHY IP.
0x042 [1:0]
WO
reset_control
(write) Writing a 1 to bit 0 initiates a TX digital
reset using the reset controller module.
The reset affects channels enabled in the
reset_ch_bitmask
. Writing a 1 to bit 1
initiates a RX digital reset of channels
enabled in the
reset_ch_bitmask
.
RO
reset_status
(read) Reading bit 0 returns the status of the
reset controller TX ready bit. Reading bit
1 returns the status of the reset
controller RX ready bit.
Reset Controls -Manual Mode
0x044
- RW
reset_fine_control You can use the
reset_fine_control
register to create your own reset
sequence. The reset control module,
illustrated in Transceiver PHY Top-
Level Modules, performs a standard
reset sequence at power on and
whenever the
phy_mgmt_clk_reset
is
asserted. Bits [31:4, 0] are reserved.
UG-01080
2015.01.19
Interlaken PHY Register Interface and Register Descriptions 7-17
Interlaken PHY IP Core Altera Corporation
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