Altera Transceiver PHY IP Core - Manual (Page 411)

For nonbonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces.
The MegaWizard Plug-In Manager provides informational messages on the connectivity of these
interfaces. The following example shows the messages for the Arria V Native PHY with four duplex
channels, four TX PLLs, in a nonbonded configuration.
For more information about transceiver reconfiguration refer to Transceiver Reconfiguration Controller
IP Core.
Example 13-4: Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 8 reconfiguration interfaces for connection to the
external reconfiguration controller.
Reconfiguration interface offsets 0-3 are connected to the transceiver
channels.
Reconfiguration interface offsets 4–7 are connected to the transmit PLLs.
Related Information
Transceiver Architecture in Arria V Devices
Simulation Support
The Quartus II release provides simulation and compilation support for the Arria V Native PHY IP Core.
Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II
software creates automatically when you generate your Arria V Transceiver Native PHY IP Core.
13-36 Simulation Support
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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