Altera Transceiver PHY IP Core - Manual (Page 161)

Word Addr Bits R/W Register Name Description
0x061 [31:0] RW
phy_serial_loopback
Writing a 1 to channel <
n
> puts channel
<
n
> in serial loopback mode. For informa‐
tion about pre- or post-CDR serial loopback
modes, refer to Loopback Modes.
0x064 [31:0] RW
pma_rx_set_locktodata
When set, programs the RX CDR PLL to
lock to the incoming data. Bit <
n
>
corresponds to channel <
n
>.
0x065 [31:0] RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to
lock to the reference clock. Bit <
n
>
corresponds to channel <
n
>.
0x066 [31:0] RO
pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR
PLL is locked to the RX data, and that the
RX CDR has changed from LTR to LTD
mode. Bit <
n
> corresponds to channel <
n
>.
0x067 [31:0] RO
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR
PLL is locked to the reference clock. Bit <
n
>
corresponds to channel <
n
>.
XAUI PCS
0x082
[31:4] - Reserved -
[3:0] RW
invpolarity[3:0] Inverts the polarity of corresponding bit on
the RX interface. Bit 0 maps to lane 0 and so
on. This register is only available in the hard
XAUI implementation.
To block: Word aligner.
0x083
[31:4] - Reserved -
[3:0] RW
invpolarity[3:0] Inverts the polarity of corresponding bit on
the TX interface. Bit 0 maps to lane 0 and so
on. This register is only available in the hard
XAUI implementation.
To block: Serializer.
UG-01080
2015.01.19
XAUI PHY Register Interface and Register Descriptions 6-21
XAUI PHY IP Core Altera Corporation
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