Interlaken phy tx and rx serial interface, Interlaken phy pll interface, Interlaken phy tx and rx serial interface -14 – Altera Transceiver PHY IP Core User Manual
Page 181: Interlaken phy pll interface -14
Signal Name
Direction
Description
rx_dataout_bp<n>
Input
When asserted, enables reading of data from the RX FIFO. This
signal functions as a read enable. The RX interface has a ready
latency of 1 cycle so that
rx_paralleldata<n>[63:0]
and
rx_
paralleldata<n>[65]
are valid the cycle after
rx_dataout_
bp<n>
is asserted.
In multi-lane configurations, the
rx_dataout_bp
port
signals must not be logically tied together.
This output is synchronous to the
rx_coreclkin
clock domain.
You can tie this
rx_dataout_bp<n>
RX FIFO read enable signal
to the inverted logic of the
rx_parallel_data[68]
RX FIFO
partially empty signal using the following assignment statement:
assign rx_dataout_bp[0] =! (rx_parallel_data[68]);
rx_user_clkout
Output
Master channel
rx_user_clkout
is available when you do not
create the optional
rx_coreclkin
.
Interlaken PHY TX and RX Serial Interface
This section describes the signals in the chip-to-chip serial interface.
Table 7-6: Serial Interface
Signal Name
Direction
Description
tx_serial_data
Output
Differential high speed serial output data using the
PCML I/O standard. Clock is embedded in the serial
data stream.
rx_serial_data
Input
Differential high speed serial input data using the
PCML I/O standard. Clock is recovered from the serial
data stream.
Interlaken PHY PLL Interface
This section describes the signals in the PLL interface.
7-14
Interlaken PHY TX and RX Serial Interface
UG-01080
2015.01.19
Altera Corporation
Interlaken PHY IP Core