Altera Transceiver PHY IP Core - Manual (Page 247)

Example 9-1: Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 2 reconfiguration interfaces for
connection to the external reconfiguration controller.
Reconfiguration interface offset 0 is connected to the transceiver channel.
Reconfiguration interface offset 1 is connected to the transmit PLL.
Table 9-26: Reconfiguration Interface
This interface uses the Avalon-MM PHY Management interface clock.
Signal Name Direction Description
reconfig_to_xcvr [( 70-1):
0]
Input Reconfiguration signals from the
Transceiver Reconfiguration
Controller. grows linearly with
the number of reconfiguration
interfaces.
reconfig_from_xcvr [( 46-1)
:0]
Output Reconfiguration signals to the
Transceiver Reconfiguration
Controller. grows linearly with
the number of reconfiguration
interfaces.
Transceiver dynamic reconfiguration requires that you assign the starting channel number if you are
using ×6 or ×N bonding. Logical channel 0 should be assigned to either physical transceiver channel 1 or
channel 4 of a transceiver bank. However, if you have already created a PCB with a different lane
assignment for logical lane 0, you can use the workaound shown in the following example to remove this
restriction. The example redefines the
pma_bonding_master
parameter using the Quartus II Assignment
Editor. In this example, the
pma_bonding_master
was originally assigned to physical channel 1. (The
original assignment could also have been to physical channel 4.) The to parameter reassigns the
pma_bonding_master
to the Custom PHY instance name. You must substitute the instance name from
your design for the instance name shown in quotation marks
Example 9-2: Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V
Devices for ×6 or ×N Bonding
set_parameter -name pma_bonding_master "\"1\"" -to
"|altera_xcvr_custom:my_custom_phy_inst|
sv_xcvr_custom_nr:S5|sv_xcvr_custom_native:transceiver_core|
sv_xcvr_native:gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_in
st"
Related Information
Transceiver Reconfiguration Controller to PHY IP Connectivity on page 16-56
9-34 Dynamic Reconfiguration
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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