Altera Transceiver PHY IP Core User Manual
Page 418
TX PMA Parameters
Table 14-4: TX PMA Parameters
The following table describes the TX PMA options you can specify.
For more information about the TX CMU, ATX, and fractional PLLs, refer to the Arria V GZ PLLs section in
Transceiver Architecture in Arria V GZ Devices.
Parameter
Range
Description
Enable TX PLL dynamic
reconfiguration
On/Off
When you turn this option On, you can dynamically
reconfigure the PLL to use a different reference clock
input. This option is also required to simulate TX PLL
reconfiguration. If you turn this option On, the
Quartus II Fitter prevents PLL merging by default;
however, you can specify merging using the
XCVR_TX_
PLL_RECONFIG_GROUP
QSF assignment.
Use external TX PLL
On/Off
When you turn this option On, the Native PHY does
not automatically instantiate a TX PLL. Instead, you
must instantiate an external PLL and connect it to the
ext_pll_clk[
-1 : 0]
port of the Arria V GZ
Native PHY.
Use the Arria V GZ Transceiver PLL IP Core to
instantiate a CMU or ATX PLL. Use Altera Phase-
Locked Loop (ALTERA_ PLL) Megafunction to
instantiate a fractional PLL.
Number of TX PLLs
1-4
Specifies the number of TX PLLs that can be used to
dynamically reconfigure channels to run at multiple
data rates. If your design does not require transceiver
TX PLL dynamic reconfiguration, set this value to 1.
The number of actual physical PLLs that are
implemented depends on the selected clock network.
Each channel can dynamically select between n PLLs,
where n is the number of PLLs specified for this
parameter.
Note: Refer to Transceiver Clocking in Arria V
Devices chapter for more details.
Main TX PLL logical index
0-3
Specifies the index of the TX PLL used in the initial
configuration.
Number of TX PLL reference
clocks
1-5
Specifies the total number of reference clocks that are
shared by all of the PLLs.
UG-01080
2015.01.19
PMA Parameters for Arria V GZ Native PHY
14-7
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation