Altera Transceiver PHY IP Core User Manual
Page 192
Table 8-2: PHY IP Core for PCI Express General Options
Name
Value
Description
Device family
Stratix V
Arria V GZ
Arria V GX
Arria V GT
Arria V SX
Arria V ST
Supports all Arria V and Stratix V
devices.
Number of lanes
1, 2, 4, 8
The total number of duplex lanes.
Protocol version
Gen1 (2.5 Gbps)
Gen2 (5.0 Gbps)
Gen3 (8.0 Gbps)
The Gen1 and Gen2 implement the
Intel PHY Interface for PCI Express
(PIPE) Architecture PCI Express 2.0
specification. The Gen3 implements
the PHY Interface for the PCI Express
Architecture PCI Express 3.0 specifi‐
cation.
Gen1 and Gen2 base data rate
1 × Lane rate
2 × Lane rate
4 × Lane rate
8 ×Lane rate
The base data rate is the output clock
frequency of the TX PLL. Select a
base data rate that minimizes the
number of PLLs required to generate
all the clocks required for data
transmission.
Data rate
2500 Mbps
5000 Mbps
8000 Mbps
Specifies the data rate. This
parameter is based on the Protocol
version you specify. You cannot
change it.
8-4
PHY for PCIe (PIPE) General Options Parameters
UG-01080
2015.01.19
Altera Corporation
PHY IP Core for PCI Express (PIPE)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)