Sdc timing constraints, Sdc timing constraints -29 – Altera Transceiver PHY IP Core User Manual
Page 297
Figure 11-5: Channel Placement and Available Channels in Arria V Devices
GXB_R0
GXB_R1
GXB_L0
GXB_L1
GXB_R2
GXB_L2
Devices Available
Number of Channels Per Bank
Transceiver Bank Names
5AGXB5KF40
5AGXB7KF40
5AGXA5HF35
5AGXA7HF35
5AGXB1HF35
5AGXB1HF40
5AGXB3HF35
5AGXB3HF40
5AGXB5HF35
5AGXB7HF35
5AGXA1EF31
5AGXA3EF31
PCI
e Har
d IP
PCI
e Har
d IP
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Not Available for
Deterministic
Protocols
Not Available for
Deterministic
Protocols
(1)
(1)
Note:
(1) In Arria V GZ devices, channel 1 and 2 are available for deterministic latency protocols.
SDC Timing Constraints
The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP
apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V
Native PHY for details.
UG-01080
2015.01.19
SDC Timing Constraints
11-29
Deterministic Latency PHY IP Core
Altera Corporation
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