Altera Transceiver PHY IP Core - Manual (Page 229)

Name Value Description
Enable channel interface On/Off Turn this option on to enable PLL and
datapath dynamic reconfiguration. When you
select this option, the width of
tx_parallel_
data
and
rx_parallel_data
buses increases
in the following way.
• n The
tx_parallel_data
bus is 44 bits
per lane; however, only the low-order
number of bits specified by the FPGA
fabric transceiver interface width contain
valid data for each lane.
• n The
rx_parallel_data
bus is 64 bits
per lane; however, only the low-order
number of bits specified by the FPGA
fabric transceiver interface width contain
valid data.
Related Information
General Options Parameters on page 9-3
Analog Parameters
Click the appropriate link to specify the analog options for your device:
Related Information
• Analog Settings for Arria V Devices on page 19-2
• Analog Settings for Arria V GZ Devices on page 19-11
• Analog Settings for Cyclone V Devices on page 19-26
• Analog Settings for Stratix V Devices on page 19-34
Presets for Ethernet
Presets allow you to specify a group of parameters to implement a particular protocol or application. If
you apply the presets for GIGE-1.25 Gbps or GIGE–2.5 Gbps, parameters with specific required values for
those protocols are set for you. Selecting a preset does not prevent you from changing any parameter to
meet the requirements of your design.
Table 9-11: Presets for Ethernet Protocol
Parameter Name GIGE-1.25 Gbps GIGE-2.50 Gbps
General Options Tab
Parameter validation rules GIGE GIGE
Enable bonding Off Off
FPGA fabric transceiver interface
width
8 16
9-16 Analog Parameters
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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