Altera Transceiver PHY IP Core - Manual (Page 366)

Name Direction Description
rx_10g_blk_lock
[-1:0]
Output Active-high status signal that is asserted when block
synchronizer acquires block lock. Valid for the
10GBASE-R and Interlaken protocols, and any basic
mode that uses the lock state machine to achieve and
monitor block synchronization for word alignment. Once
the block synchronizer acquires block lock, it takes at
least 16 errors for
rx_10g_blk_lock
to be deasserted.
rx_10g_blk_sh_err
[-1:0]
Output Error status signal from block synchronizer indicating an
invalid synchronization header has been received. Valid
for the 10GBASE-R and Interlaken protocols, and any
legal basic mode that uses the lock state machine to
achieve and monitor block synchronization for word
alignment. Active only after block lock is achieved. This
signal is generated by
rx_pma_clk
and is pulse-stretched
by 3 clock cycles. You must use a synchronizer.
Bit-Slip Gearbox Feature Synchronizer
rx_10g_bitslip
[-1:0]
Input User control bit-slip in the RX Gearbox. Slips one bit per
rising edge pulse.
tx_10g_bitslip
[7-1:0]
Input TX bit-slip is controlled by
tx_bitslip
port.
Shifts the number of bit location specified by
tx_
bitslip
. The maximum shift is .
64b/66b
rx_10g_clr_errblk_count
[-1:0]
Input For the 10GBASE-R protocol, asserted to clear the error
block counter which counts the number of times the RX
state machine enters the RX error state.
BER
rx_10g_highber
[-1:0]
Output For the 10GBASE-R protocol, status signal asserted to
indicate a bit error ratio of >10 -4 . A count of 16 in 125us
indicates a bit error ratio of >10 –4 . Once asserted, it
remains high for at least 125 us.
rx_10g_clr_highber_cnt
[-1:0]
Input For the 10GBASE-R protocol, status signal asserted to
clear the BER counter which counts the number of times
the BER state machine enters the BER_BAD_SH state.
This signal has no effect on the operation of the BER state
machine.
PRBS
rx_10g_prbs_done Output When asserted, indicates the verifier has aligned and
captured consecutive PRBS patterns and the first pass
through a polynomial is complete.
12-68 10G PCS Interface
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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