Altera Transceiver PHY IP Core User Manual
Page 453
Gearbox
The gearbox adapts the PMA data width to a wider PCS data width when the PCS is not two or four times
the PMA width.
Table 14-34: Gearbox Parameters
Parameter
Range
Description
Enable TX data polarity inversion
On/Off
When you turn this option On, the
gearbox inverts the polarity of TX data
allowing you to correct incorrect
placement and routing on the PCB.
Enable TX data bitslip
On/Off
When you turn this option On, the TX
gearbox operates in bitslip mode.
Enable RX data polarity inversion
On/Off
When you turn this option On, the
gearbox inverts the polarity of RX data
allowing you to correct incorrect
placement and routing on the PCB.
Enable RX data bitslip
On/Off
When you turn this option On, the 10G
PCS RX block synchronizer operates in
bitslip mode.
Enable tx_10g_bitslip port
On/Off
When you turn this option On, the 10G
PCS includes the
tx_10g_bitslip
input
port. The data slips 1 bit for every
positive edge of the
tx_10g_bitslip
input. The maximum shift is <
pcswidth> -1 bits, so that if the PCS is 64
bits wide, you can shift 0-63 bits.
Enable rx_10g_bitslip port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_bitslip
input
port. The data slips 1 bit for every
positive edge of the
rx_10g_bitslip
input. he maximum shift is < pcswidth>
-1 bits, so that if the PCS is 64 bits wide,
you can shift 0-63 bits.
PRBS Verifier
You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks
support the following patterns:
• Pseudo-random binary sequence (PRBS)
• Pseudo-random pattern
• Square wave
14-42
10G PCS Parameters for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation
Arria V GZ Transceiver Native PHY IP Core