Altera Transceiver PHY IP Core User Manual
Page 164
Word Addr
Bits
R/W
Register Name
Description
0x088
[31:8]
-
Reserved
-
[7:4]
R,
sticky
rmfifofull[3:0]
When asserted, indicates that rate match
FIFO is full (20 words). Bits 0-3 correspond
to lanes 0-3, respectively. Reading the value
of the
rmfifofull
register clears the bits.
This register is only available in the hard
XAUI implementation
From block: Rate match FIFO.
[3:0]
rmfifoempty[3:0]
When asserted, indicates that the rate match
FIFO is empty (5 words). Bits 0-3
correspond to lanes 0-3, respectively.
Reading the value of the
rmfifoempty
register clears the bits. This register is only
available in the hard XAUI implementation
From block: Rate match FIFO.
0x089
[31:3]
-
Reserved
-
[2:0]
R,
sticky
phase_comp_fifo_error[2:0]
Indicates a TX phase compensation FIFO
overflow or
underrun
condition on the
corresponding lane. Reading the value of the
phase_comp_fifo_error
register clears the
bits. This register is only available in the
hard XAUI implementation
From block: TX phase compensation FIFO.
0x08a [0]
RW
simulation_flag
Setting this bit to 1 shortens the duration of
reset and loss timer when simulating. Altera
recommends that you keep this bit set
during simulation.
For more information about the individual PCS blocks, refer to the Transceiver Architecture chapters of
the appropriate device handbook.
Related Information
•
•
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Transceiver Architecture in Arria V Devices
•
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6-24
XAUI PHY Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation
XAUI PHY IP Core