Altera Transceiver PHY IP Core - Manual (Page 249)

Device Family Support
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
The following table shows the level of support offered by the Low Latency PHY IP Core for Altera device
families.
Table 10-1: Device Family Support
Device Family Support
Arria V GZ devices Final
Stratix V devices Final
Other device families No support
Performance and Resource Utilization
The following table shows the typical expected device resource utilization for different configurations
using the current version of the Quartus II software targeting a Stratix V GX (5SGSMD612H35C2) device.
Table 10-2: Low Latency PHY Performance and Resource Utilization—Stratix V GX Device
Implementa‐
tion
Number of
Lanes
Serialization
Factor
Worst-Case
Frequency
Combinational
ALUTs
Dedicated
Registers
Memory Bits
11 Gbps 1 32 or 40 599.16 112 95 0
11 Gbps 4 32 or 40 584.8 141 117 0
11 Gbps 10 32 or 40 579.71 192 171 0
6 Gbps
(10 Gbps
datapath)
1 32 or 40 608.27 111 93 0
6 Gbps
(10 Gbps
datapath)
4 32 or 40 454.96 141 117 0
6 Gbps
(10 Gbps
datapath)
10 32 or 40 562.75 192 171 0
10-2 Device Family Support
UG-01080
2015.01.19
Altera Corporation Low Latency PHY IP Core
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