Altera Transceiver PHY IP Core - Manual (Page 420)

Parameter Range Description
Selected reference clock
source
0-4 You can define up to 5 frequencies for the PLLs in
your core. The Reference clock frequency selected
for index 0 , is assigned to TX PLL<0>. The Reference
clock frequency selected for index 1 , is assigned to
TX PLL<1>, and so on.
RX CDR Options
Table 14-6: RX PMA Parameters
The following table describes the RX CDR options you can specify. For more information about the CDR
circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Arria V Devices.
Parameter Range Description
Enable CDR dynamic
reconfiguration
On/Off
When you turn this option On, you can dynamically
change the reference clock input the CDR circuit.
This option is also required to simulate TX PLL
reconfiguration.
Number of CDR reference
clocks
1-5 Specifies the number of reference clocks for the
CDRs.
Selected CDR reference clock 0-4 Specifies the index of the selected CDR reference
clock.
Selected CDR reference clock
frequency
Device Dependent Specifies the frequency of the clock input to the CDR.
PPM detector threshold +/- 1000 PPM Specifies the maximum PPM difference the CDR can
tolerate between the input reference clock and the
recovered clock.
Enable rx_pma_clkout port On/Off When you turn this option On, the RX parallel clock
which is recovered from the serial received data is an
output of the PMA.
Enable rx_is_lockedtodata
port
On/Off
When you turn this option On, the
rx_is_lockedto-
data
port is an output of the PMA.
Enable rx_is_lockedtoref
port
On/Off When you turn this option On, the
rx_is_
lockedtoref
port is an output of the PMA.
Enable rx_set_lockedtodata
and rx_set_locktoref ports
On/Off When you turn this option On, the
rx_set_lockedt-
data
and rx_set_lockedtoref ports are outputs of the
PMA.
Enable rx_clkslip port On/Off When you turn this option On, the
rx_clkslip
control input port is enabled. The deserializer slips
one clock edge each time this signal is asserted. You
can use this feature to minimize uncertainty in the
serialization process as required by protocols that
require a datapath with deterministic latency such as
CPRI.
UG-01080
2015.01.19
PMA Parameters for Arria V GZ Native PHY 14-9
Arria V GZ Transceiver Native PHY IP Core Altera Corporation
Send Feedback