Altera Transceiver PHY IP Core - Manual (Page 511)

RX Data Word Description
rx_parallel_data[12]
Pattern detect
rx_parallel_data[14:13]
The following encodings are defined:
• 2’b00: Normal data
• 2’b01: Deletion
• 2’b10: Insertion (or Underflow with 9’h1FE or
9’h1F7)
• 2’b11: Overflow
rx_parallel_data[15]
Running disparity value
Table 15-20: Location of Valid Data Words for rx_parallel_data for Various FPGA Fabric to PCS
Parameterizations
The following table shows the valid 16-bit data words with and without the byte deserializer for single- and
double-word FPGA fabric to PCS interface widths.
Configuration Bus Used Bits
Single word data bus, byte deserializer disabled [15:0] (word 0)
Single word data bus, byte serializer enabled [47:32], [15:0] (words 0 and 2)
Double word data bus, byte serializer disabled [31:0] (words 0 and 1)
Double word data bus, byte serializer enabled [63:0] (words 0-3)
Related Information
• Timing Constraints for Bonded PCS and PMA Channels on page 17-10
• Transceiver Architecture in Cyclone V Devices
• Transceiver Architecture in Cyclone V Devices
Cyclone V Standard PCS Interface Ports
This section describes the signals that comprise the Standard PCS interface.
15-28 Cyclone V Standard PCS Interface Ports
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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