Altera Transceiver PHY IP Core User Manual
Page 460
Name
Direction
Description
tx_parallel_data
[
Input
PCS TX parallel data. Used when you enable
either the Standard or 10G datapath. For the
Standard datapath, if you turn on Enable
simplified data interface , tx_parallel_data
includes only the data and control signals
necessary for the current configuration.
Dynamic reconfiguration of the interface is not
supported. For the 10G PCS, if the parallel data
interface is less than 64 bits wide, the low-order
bits of tx_parallel_data are valid. For the 10G
PCS operating in 66:40 Basic mode, the 66 bus
is formed as follows: { tx_parallel_
data[63:0],tx_10g_control[0], tx_10g_
control[1]}.
For the Standard PCS, refer to
for
for various
parameterizations.
rx_parallel_data
[
Output
PCS RX parallel data. Used when you enable
either the Standard or 10G datapath. For the
Standard datapath, if you turn on Enable
simplified data interface , rx_parallel_data
includes only the data and control signals
necessary for the current configuration.
Dynamic reconfiguration of the interface is not
supported. For the 10G PCS, if the parallel data
interface is less than 64 bits wide, the low-order
bits of rx_parallel_data are valid. For the 10G
PCS operating in 66:40 mode, the 66 bus is
formed as follows: { rx_parallel_data[63:0],rx_
10g_control[0], rx_10g_control[1]}.
For the Standard PCS, refer to
for
for various
parameterizations.
QPI
tx_pma_qpipullup
Input
Control input port for Quick Path Interconnect
(QPI) applications. When asserted, the
transmitted pulls the output signal to high state.
Use this port only for QPI applications.
tx_pma_qpipulldn
Input
Control input port for Quick Path Interconnect
(QPI) applications. This is an active low signal.
When asserted, the transmitter pulls the output
signal to low state. Use this port only for QPI
applications.
UG-01080
2015.01.19
Common Interface Ports for Arria V GZ Native PHY
14-49
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation