Altera Transceiver PHY IP Core User Manual
Page 678
Date
Document
Version
Changes Made
March 2013
2.0
Made the following changes:
• Improved the description of automatic speed detection.
• Updated speed grade information.
• Updated definition of
KR AN Link Ready[5:0]
to include
1000BASE-KX.
• Added the following registers
SEQ LT timeout
at 0xB1, Bit 2
and
SEQ Reconfig Mode[5:0]
0xB1, Bits[13:8] registers
• Revised Functional Description section.
• Corrected typos in specifications of address bits
Ovride LP
Coef enable
,
Updated TX Coef new
and
Updated RX coef
new
.
• Corrected encodings for
ber_time_k_frames
,
ber_time_
frames
and
ber_time_m_frames
.
1Gbe/10GbE
March 2013
2.0
Made the following changes:
• Updated speed grade information.
• Removed definition of
Disable AN Timer
bit. It is not used for
this variant.
• Added fact that
RESTART_AUTO_NEGOTIATION
bit is self-clearing
(0x90, bit 9)
• Added fact that half-duplex mode is not supported. (0x94, bit 6)
• Added fact that the next page bit is not supported. (0x94, bit 15)
XAUI
March 2013
2.0
Added Arria V, Arria V GZ and Cyclone V to the list of devices that
do not support the
pma_tx_pll_is_locked
register in Table 6-15:
XAUI PHY IP Core Registers.
Interlaken
March 2013
2.0
No changes from previous release.
PHY IP Core for PCI Express
March 2013
2.0
Added SDC constraints for Gen3 clocking.
Custom PHY
March 2013
2.0
No changes from previous release.
Low Latency PHY
March 2013
2.0
No changes from previous release.
Deterministic Latency PHY
March 2013
2.0
No changes from previous release.
21-18
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core