Altera Transceiver PHY IP Core - Manual (Page 196)

Signal Name Direction Description
tx_blk_start
Input For Gen3, specifies start block byte location for TX
data in the 128-bit block data. Used when the
interface between the PCS and PHY MAC is 32
bits. Not used for the Gen1 and Gen2 data rates.
tx_sync_hdr[1:0]
Input
For Gen3, indicates whether the 130-bit block
being transmitted is a Data or Control Ordered Set
Block. The following encodings are defined:
• 2'b10: Data block
• 2'b01: Control Ordered Set Block
This value is read when
tx_blk_start
= 1b’1.
Refer to “Section 4.2.2.1. Lane Level Encoding” in
the PCI Express Base Specification, Rev. 3.0 for a
detailed explanation of data transmission and
reception using 128b/130b encoding and decoding.
Not used for the Gen1 and Gen2 data rates.
pipe_txdetectrx_loopback
Input This signal instructs the PHY to start a receive
detection operation. After power-up asserting this
signal starts a loopback operation. Refer to section
6.4 of the Intel PHY Interface for PCI Express
(PIPE) for a timing diagram.
pipe_txelecidle
Input This signal forces the transmit output to electrical
idle. Refer to section 7.3 of the Intel PHY Interface
for PCI Express (PIPE) for timing diagrams.
pipe_powerdown[1:0]
Input
This signal requests the PHY to change its power
state to the specified state. The following encodings
are defined:
• 2’b00– P0, normal operation
• 2’b01–P0s, low recovery time latency, power
saving state
• 2’b10–P1, longer recovery time (64 us
maximum latency), lower power state
• 2’b11–P2, lowest power state. (not supported)
pipe_txdeemph
Input
Transmit de-emphasis selection. In PCI Express
Gen2 (5 Gbps) mode it selects the transmitter de-
emphasis:
• 1'b0: -6 dB
• 1'b1: -3.5 dB
8-8 PHY for PCIe (PIPE) Input Data from the PHY MAC
UG-01080
2015.01.19
Altera Corporation PHY IP Core for PCI Express (PIPE)
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