Xaui phy ports, Xaui phy ports -10 – Altera Transceiver PHY IP Core User Manual
Page 150
XAUI PHY Ports
This section describes the ports for the IP core.
illustrates the top-level signals of the XAUI PHY IP Core for the hard IP implementation. This
variant is available for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV GX devices.
illustrates the top-level signals of the XAUI PHY IP Core for the soft IP implementation. With the
exception of the optional signals available for debugging and the signals for dynamic reconfiguration of
the transceivers, the top-level signals of the two variants is nearly identical. The DDR XAUI soft IP signals
and behavior are the same as the soft IP implementation.
The block diagram shown in the MegaWizard Plug-In Manager GUI labels the external pins with the
interface type and places the interface name inside the box. The interface type and name are used to define
component interfaces in the _hw.tcl. If you turn on Show signals, the block diagram displays all top-level
signal names.
For more information about _hw.tcl files refer to refer to the Component Interface Tcl Reference chapter
in volume 1 of the Quartus II Handbook.
Figure 6-3: XAUI Top-Level Signals–Hard IP PCS and PMA
xgmii_tx_dc[71:0]
xgmii_tx_clk
xgmii_rx_dc[71:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
rx_analogreset
rx_digitalreset
tx_digitalreset
XAUI Top-Level Signals Hard IP Implementation
PMA
Channel
Controller
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
rx_invpolarity[3:0]
rx_set_locktodata[3:0]
rx_is_lockedtodata[3:0]
rx_set_locktoref[3:0]
rx_is_lockedtoref[3:0]
tx_invpolarity[3:0]
rx_seriallpbken[3:0]
rx_channelaligned[3:0]
rx_rmfifoempty[3:0]
rx_rmfifofull[3:0]
rx_disperr[7:0]
rx_errdetect[7:0]
rx_patterndetect[7:0]
rx_rmfifodatadeleted[7:0]
rx_rmfifodatainserted[7:0]
rx_runningdisp[7:0]
rx_syncstatus[7:0]
rx_phase_comp_fifo_error[3:0]
tx_phase_comp_fifo_error[3:0]
rx_rlv[3:0]
rx_recovered_clk[3:0]
reconfig_to_xcvr[3:0]
reconfig_from_xcvr[16:0]
cal_blk_powerdown
gxb_powerdown
pll_powerdown
pll_locked
rx_ready
tx_ready
Transceiver
Serial Data
Rx and Tx
Status
All Optional
SDR Tx XGMII
SDR Rx XGMII
Avalon-MM PHY
Management
Interface
Clock
and
Reset
Optional
Resets
Transceiver
Reconfiguration
(Optional)
Optional
6-10
XAUI PHY Ports
UG-01080
2015.01.19
Altera Corporation
XAUI PHY IP Core