Altera Transceiver PHY IP Core - Manual (Page 410)

Example 13-1: Using the set_false_path Constraint to Identify Asynchronous Inputs
set_false_path -through {*8gbitslip*} -to [get_registers
*8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gbytordpld*} -to [get_registers
*8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gcmpfifoburst*} -to [get_registers
*8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gphfifoburstrx*} -to [get_registers
*8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gsyncsmen*} -to [get_registers
*8g*pcs*SYNC_DATA_REG*]
set_false_path -through {*8gwrdisablerx*} -to [get_registers
*8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*rxpolarity*} -to [get_registers *SYNC_DATA_REG*]
set_false_path -through {*pldeidleinfersel*} -to [get_registers
*SYNC_DATA_REG*]
• You can use the
set_max_delay
constraint on a given path to create a constraint for asynchronous
signals that do not have a specific clock relationship but require a maximum path delay.
Example 13-2: Using the max_delay Constraint to Identify Asynchronous Inputs
# Example: Apply 10ns max delay
set_max_delay -from *tx_from_fifo* -to *8g*pcs*SYNC_DATA_REG1 10
• You can use the
set_false
path command only during Timequest timing analysis.
Example 13-3: Using the set_false TimeQuest Constraint to Identify Asynchronous Inputs
#if {$::TimeQuestInfo(nameofexecutable) eq "quartus_fit"} {
#} else {
#set_false_path -from [get_registers {*tx_from_fifo*}] -through
{*txbursten*} -to [get_registers *8g_*_pcs*SYNC_DATA_REG
Note: In in all of these examples, you must substitute you actual signal names for the signal names
shown.
Dynamic Reconfiguration
Dynamic reconfiguration calibrates each channel to compensate for variations due to process, voltage,
and temperature (PVT).
As silicon progresses towards smaller process nodes, circuit performance is affected more by variations
due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can
be offset from required ranges. The calibration performed by the dynamic reconfiguration interface
compensates for variations due to PVT.
UG-01080
2015.01.19
Dynamic Reconfiguration 13-35
Arria V Transceiver Native PHY IP Core Altera Corporation
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