Altera Transceiver PHY IP Core - Manual (Page 185)

Word Addr Bits R/W Register Name Description
The Interlaken PHY IP requires the use
of the embedded reset controller to
initiate the correct the reset sequence. A
hard reset to
phy_mgmt_clk_reset
and
mgmt_rst_reset
is required for
Interlaken PHY IP.
Altera does not recommend use of a soft
reset or the use of these reset register bits
for Interlaken PHY IP.
[3] RW
reset_rx_digital
Writing a 1 causes the RX digital reset
signal to be asserted, resetting the RX
digital channels enabled in
reset_ch_
bitmask
. You must write a 0 to clear the
reset condition.
[2] RW
reset_rx_analog
Writing a 1 causes the internal RX
digital reset signal to be asserted,
resetting the RX analog logic of all
channels enabled in
reset_ch_bitmask
.
You must write a 0 to clear the reset
condition.
[1] RW
reset_tx_digital
Writing a 1 causes the internal TX
digital reset signal to be asserted,
resetting all channels enabled in
reset_
ch_bitmask
. You must write a 0 to clear
the reset condition.
PMA Control and Status Registers
0x061 [31:0] RW
phy_serial_loopback
Writing a 1 to channel <
n
> puts channel
<
n
> in serial loopback mode. For
information about pre- or post-CDR
serial loopback modes, refer to
Loopback Modes.
0x064 [31:0] RW
pma_rx_set_
locktodata
When set, programs the RX CDR PLL to
lock to the incoming data. Bit <
n
>
corresponds to channel <
n
>. By default,
the Interlaken PHY IP configures the
CDR PLL in Auto lock Mode. This bit is
part of the CDR PLL Manual Lock Mode
which is not the recommended usage.
7-18 Interlaken PHY Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation Interlaken PHY IP Core
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