Altera Transceiver PHY IP Core - Manual (Page 606)

Options
• 85_Ohms
• 100_Ohms
• 120_Ohms
• 150_Ohms
• External_Resistor
Assign To
Pin - TX & RX serial data
XCVR_REFCLK_PIN_TERMINATION
Pin Planner and Assignment Editor Name
Transceiver Dedicated Refclk Pin Termination
Description
Specifies the intended termination value for the specified refclk pin. The following 3 settings are available:
• AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled
signals. This setting implements on-chip termination and on-chip signal biasing.
• DC_COUPLING_ INTERNAL_100_OHMS: Used this setting when the dedicated transceiver
reference clock pins are fed by a DC coupled signal whose V
cm
meets the device specification. This
assignment implements internal on-chip termination but not on-chip signal biasing.
• DC_COUPLING_EXTERNAL_RESISTOR: Use this assignment when the dedicated transceiver
reference clock pins are fed by a DC coupled signal. This option does not implement internal on-chip
termination or signal biasing. You must implement termination and signal biasing outside of the
FPGA. This assignment is recommended for compliance with the PCI Express Card Electromechanical
Specification Rev. 2.0 and the HCSL IO Standard.
Options
• AC_COUPLING
• DC_COUPLING_INTERNAL_100_OHMS
• DC_COUPLING_EXTERNAL_RESISTOR
Assign To
Pin - PLL refclk pin
XCVR_RX_BYPASS_EQ_STAGES_234
Pin Planner and Assignment Editor Name
Receiver Equalizer Stage 2, 3, 4 Bypass
Description
Bypass continuous time equalizer stages 2, 3, and 4 to save power. This setting eliminates significant AC
gain on the equalizer and is appropriate for chip-to-chip short range communication on a PCB. Assigning
19-12 XCVR_REFCLK_PIN_TERMINATION
UG-01080
2015.01.19
Altera Corporation Analog Parameters Set Using QSF Assignments
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