Altera Transceiver PHY IP Core - Manual (Page 120)

Signal Name Direction Description
led_disp_err Output Disparity error signal indicating a 10-bit running
disparity error. Asserted for one
rx_clkout_1g
cycle when a disparity error is detected. A running
disparity error indicates that more than the
previous and perhaps the current received group
had an error.
led_an Output Clause 37 Auto-negotiation status. The PCS
function asserts this signal when auto-negotiation
completes.
XGMII Mapping to Standard SDR XGMII Data
Table 5-8: TX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name SDR XGMII Signal Name Description
xgmii_tx_dc[7:0] xgmii_sdr_data[7:0]
Lane 0 data
xgmii_tx_dc[8] xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_tx_dc[16:9] xgmii_sdr_data[15:8]
Lane 1 data
xgmii_tx_dc[17] xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_tx_dc[25:18] xgmii_sdr_data[23:16]
Lane 2 data
xgmii_tx_dc[26] xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_tx_dc[34:27] xgmii_sdr_data[31:24]
Lane 3 data
xgmii_tx_dc[35] xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_tx_dc[43:36] xgmii_sdr_data[39:32]
Lane 4 data
xgmii_tx_dc[44] xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_tx_dc[52:45] xgmii_sdr_data[47:40]
Lane 5 data
xgmii_tx_dc[53] xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_tx_dc[61:54] xgmii_sdr_data[55:48]
Lane 6 data
xgmii_tx_dc[62] xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_tx_dc[70:63] xgmii_sdr_data[63:56]
Lane 7 data
xgmii_tx_dc[71] xgmii_sdr_ctrl[7]
Lane 7 control
UG-01080
2015.01.19
XGMII Mapping to Standard SDR XGMII Data 5-11
1G/10 Gbps Ethernet PHY IP Core Altera Corporation
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