Altera Transceiver PHY IP Core User Manual
Page 309
Parameter
Range
Description
Enable rx_clkslip port
On/Off
When you turn this option On, the
rx_clkslip
control input port is enabled. The deserializer slips
one clock edge each time this signal is asserted. You
can use this feature to minimize uncertainty in the
serialization process as required by protocols that
require a datapath with deterministic latency such as
CPRI.
Enable rx_seriallpbken port
On/Off
When you turn this option On, the
rx_seriallpbken
is an input to the core. When your drive a 1 on this
input port, the PMA operates in loopback mode with
TX data looped back to the RX channel.
The following table lists the best case latency for the most significant bit of a word for the RX deserializer
for the PMA Direct datapath. For example, for an 8-bit interface width, the latencies in UI are 11 for bit 7,
12 for bit 6, 13 for bit 5, and so on.
Table 12-8: Latency for RX Deserialization in Stratix V Devices
FPGA Fabric Interface Width
Stratix V Latency in UI
8 bits
11
10 bits
13
16 bits
19
20 bits
23
32 bits
35
40 bits
43
64 bits
99
80 bits
123
Table 12-9: Latency for TX Serialization in Stratix V Devices
The following table lists the best- case latency for the LSB of the TX serializer for all supported interface widths for
the PMA Direct datapath.
FPGA Fabric Interface Width
Stratix V Latency in UI
8 bits
44
10 bits
54
16 bits
68
20 bits
84
32 bits
100
40 bits
124
64 bits
132
80 bits
164
UG-01080
2015.01.19
PMA Parameters for Stratix V Native PHY
12-11
Stratix V Transceiver Native PHY IP Core
Altera Corporation