Altera Transceiver PHY IP Core - Manual (Page 182)

Table 7-7: PLL Interface
Signal Name Direction Description
pll_ref_clk
Input
Reference clock for the PHY PLLs. Refer to the Lane
rate entry in the Table 7-2 table for required frequen‐
cies.
Custom, user-defined, data rates are now supported.
However, the you must choose a lane data rate that
results in standard board oscillator reference clock
frequency to drive the
pll_ref_clk
and meet jitter
requirements. Choosing a lane data rate that deviates
from standard reference clock frequencies may result
in custom board oscillator clock frequencies which
could be unavailable or cost prohibitive.
Interlaken Optional Clocks for Deskew
This section describes the optional clocks that you can create to reduce clock skew.
Table 7-8: Deskew Clocks
Signal Name Direction Description
tx_coreclkin
Input When enabled
tx_coreclkin
is available as input port
which drives the write side of TX FIFO. Altera
recommends using this clock to reduce clock skew.
The minimum frequency is data rate/67. Using a lower
frequency will underflow the TX FIFO causing the
Frame Generators to go into a unrecoverable out of
alignment state and insert Skip Words into the lane. If
the Interlaken TX FIFO underflows, the alignment
state machine tries to recover continuously. When
disabled,
tx_clkout
drives the write side the TX FIFO.
tx_coreclkin
must be used when the number of lanes
is greater than 1.
rx_coreclkin
Input When enabled,
rx_coreclkin
is available as input
port which drives the read side of RX FIFO. Altera
recommends using this clock to reduce clock skew.
You should use a minimum frequency of lane data
rate/ 67 to drive
rx_coreclkin
. Using a lower
frequency overflows the RX FIFO corrupting the
received data.When disabled,
rx_user_clkout
, which
is the master
rx_clkout
for all the bonded receiver
lanes, is internally routed to drive the read side the RX
FIFO.
UG-01080
2015.01.19
Interlaken Optional Clocks for Deskew 7-15
Interlaken PHY IP Core Altera Corporation
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