6/×n bonded clocking, 6/×n bonded clocking -69 – Altera Transceiver PHY IP Core User Manual
Page 367
Name
Direction
Description
rx_10g_prbs_err
Output
When asserted, indicates an error only after the
rx_10g_
prbs_done
signal has been asserted. This signal pulses for
every error that occurs. An error can only occur once per
word. This signal indicates errors for both the PRBS and
pseudo-random patterns. Synchronous to
rx_10g_
coreclkin
.
rx_10g_prbs_err_clr
Input
When asserted, clears the PRBS pattern and de-asserts the
rx_10g_prbs_done
signal. Synchronous to
rx_10g_
coreclkin
.
×6/×N Bonded Clocking
The Native PHY supports bonded clocking in which a single TX PLL generates the clock that drives the
transmitter for up to 27 contiguous channels. Bonded configurations conserve PLLs and reduce channel-
to-channel clock skew. Bonded channels do not support dynamic reconfiguration of the transceiver.
When you specify ×6/×N bonding, the transceiver channels that reside in the same bank as the TX PLL
are driven over the x6 clock line. Channels outside of the this bank are driven on the ×N clock lines, as the
following figure illustrates.
UG-01080
2015.01.19
×6/×N Bonded Clocking
12-69
Stratix V Transceiver Native PHY IP Core
Altera Corporation