Interlaken phy timequest timing constraints, Interlaken phy timequest timing constraints -21 – Altera Transceiver PHY IP Core User Manual
Page 188
Signal Name
Direction
Description
reconfig_from_xcvr
[(
Output
Reconfiguration signals to the Transceiver Reconfiguration
Controller. <
n
> grows linearly with the number of reconfigura‐
tion interfaces. <
n
> initially includes the total number
transceiver channels before optimization/merging.
Note: Transceiver dynamic reconfiguration requires that you assign the starting channel number.
Interlaken PHY TimeQuest Timing Constraints
This section describes the Interlaken PHY TimeQuest timing constraints.
You must add the following TimeQuest constraint to your Synopsys Design Constraints File (.sdc) timing
constraint file:
derive_pll_clocks -create_base_clocks
Note: The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY
IP apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of
Stratix V Native PHY for details.
Related Information
SDC Timing Constraints of Stratix V Native PHY
on page 12-74
This section describes SDC examples and approaches to identify false timing paths.
Interlaken PHY Simulation Files and Example Testbench
This section describes the Interlaken PHY simulation files and example testbench.
Refer to “ Running a Simulation Testbench” for a description of the directories and files that the Quartus
II software creates automatically when you generate your Interlaken PHY IP Core.
Refer to the Altera Wiki for an example testbench that you can use as a starting point in creating your
own verification environment.
Related Information
•
Running a Simulation Testbench
•
UG-01080
2015.01.19
Interlaken PHY TimeQuest Timing Constraints
7-21
Interlaken PHY IP Core
Altera Corporation