Figure 4-8: fec codeword format – Altera Transceiver PHY IP Core User Manual
Page 73
Figure 4-8: FEC Codeword Format
64 Bit Payload Word 0
64 Bit Payload Word 4
64 Bit Payload Word 8
64 Bit Payload Word 12
64 Bit Payload Word 16
64 Bit Payload Word 20
64 Bit Payload Word 24
64 Bit Payload Word 28
T
0
T
4
T
8
T
12
T
16
T
20
T
24
T
28
64 Bit Payload Word 1
64 Bit Payload Word 5
64 Bit Payload Word 9
64 Bit Payload Word 13
64 Bit Payload Word 17
64 Bit Payload Word 21
64 Bit Payload Word 25
64 Bit Payload Word 29
T
1
T
5
T
9
T
13
T
17
T
21
T
25
T
29
64 Bit Payload Word 2
64 Bit Payload Word 6
64 Bit Payload Word 10
64 Bit Payload Word 14
64 Bit Payload Word 18
64 Bit Payload Word 22
64 Bit Payload Word 26
64 Bit Payload Word 30
T
2
T
6
T
10
T
14
T
18
T
22
T
26
T
30
64 Bit Payload Word 3
64 Bit Payload Word 7
64 Bit Payload Word 11
64 Bit Payload Word 15
64 Bit Payload Word 19
64 Bit Payload Word 23
64 Bit Payload Word 27
64 Bit Payload Word 31
T
3
T
7
T
11
T
15
T
19
T
23
T
27
T
31
32 Parity Bits
Total Block Length = (32 x 65) + 32 = 2,112 Bits
Error detection and correction consists of calculating the syndrome of the received codeword. The
syndrome is the remainder from the polynomial division of the received codeword by g(x). If the
syndrome is zero, the codeword is correct. If the syndrome is non-zero, you can use it to determine the
most likely error.
Figure 4-9: Codewords, Parity and Syndromes
Data
Parity
Codeword
Rem of Divide
by g(x)
Syndrome
The Syndrome Is Also
Equal to the Local Parity
XOR Received Parity
Syndrome = 0 If the
Codeword Is Good
TX FEC Module Scrambler
In addition to the TX FEC encoder, the TX FEC module includes the following functions:
• FEC Scrambler: The FEC scrambler scrambles the encoded output. The polynomial used to scramble
the encoded output ensures DC balance to facilitate block synchronization at the receiver. It is shown
below.
X = x
58
+ X
39
+ 1
• FEC Gearbox: The FEC gearbox adapts the FEC data width to the smaller bus width of the interface to
the PCS. It supports a special 65:64 gearbox ratio.
RX FEC Module
The RX FEC module is clocked at 161.1 MHz. It includes the following functions:
UG-01080
2015.01.19
Forward Error Correction (Clause 74)
4-17
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
Altera Corporation