Altera Transceiver PHY IP Core - Manual (Page 270)

Figure 11-1: Deterministic Latency PHY IP Core
Deterministic Latency PHY IP Core
Arria V, Cyclone V, or Stratix V FPGA
PCS:
Phase Comp FIFOs
Byte Serializer/
Deserializer
8B/10B
Word Aligner
Bit Slipper
PMA:
CDR
Serializer
Deserializer
TX Serial Data
RX Serial Data
to
Optical
Link
Avalon-ST TX and RX
Avalon-MM Cntrl and Status
to and from
Transceiver Reconfiguration
Controller
The data that the Deterministic Latency PHY receives data on its FPGA fabric interface employs the
Avalon Streaming (Avalon-ST) protocol to transmit and receive data. The Avalon-ST protocol is a simple
protocol designed for driving high bandwidth, low latency, unidirectional data. The Deterministic Latency
PHY IP Core also includes an Avalon Memory-Mapped (Avalon-MM) interface to access control and
status registers. This is a standard, memory-mapped protocol that is normally used to read and write
registers and memory. The transceiver reconfiguration interface connects to the Altera Transceiver
Reconfiguration Controller IP Core which can dynamically reconfigure transceiver settings. Finally, the
PMA transmits and receives serial data.
Related Information
• Implementing the CPRI Protocol Using the Deterministic PHY IP Core
• Avalon Interface Specifications
Deterministic Latency Auto-Negotiation
The Deterministic Latency PHY IP Core supports auto-negotiation. When required, the channels
initialize at the highest supported frequency and switch to successively lower data rates if frame
synchronization is not achieved.
If your design requires auto-negotiation, choose a base data rate that minimizes the number of PLLs
required to generate the clocks required for data transmission. By selecting an appropriate base data rate,
you can change data rates by changing the divider used by the clock generation block. The following table
shows an example where setting two base data rates, 4915.2 and 6144 Mbps, with the appropriate clock
dividers generates almost the full range of data rates required by the CPRI protocol.
Table 11-1: Recommended Base Data Rate and Clock Divisors for CPRI
Data Rate (Mbps)
Base Data Rate (Mbps) Clock Divider
614.4 4915.2 8
1228.8 4915.2 4
11-2 Deterministic Latency Auto-Negotiation
UG-01080
2015.01.19
Altera Corporation Deterministic Latency PHY IP Core
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