Altera LVDS SERDES Transmitter / Receiver - Manual

LVDS SERDES Transmitter/Receiver IP Cores User
Guide
2014.12.15
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The low-voltage differential signaling serializer or deserializer (LVDS SERDES) megafunction IP cores
(ALTLVDS_TX and ALTLVDS_RX) implement the LVDS SERDES interfaces to transmit and receive
high-speed differential data. You can configure the features of these IP cores with the IP Catalog and
parameter editor.
Features
The following table lists the features of the ALTLVDS_TX and ALTLVDS_RX IP cores.
Table 1: ALTLVDS_TX and ALTLVDS_RX Features
Features Supported devices
ALTLVDS_TX and ALTLVDS_RX
Parameterizable data channel widths All Arria ® , Cyclone ® , and Stratix ® series devices.
Parameterizable serializer/deserializer
(SERDES) factors
All Arria, Cyclone, and Stratix series devices.
Registered input and output ports All Arria, Cyclone, and Stratix series devices.
Support for external phase-locked loops
(PLL)
All Arria, Cyclone, and Stratix series devices.
PLLs sharing between transmitters and
receivers
All Arria, Cyclone, and Stratix series devices.
PLL control signals All Arria, Cyclone, and Stratix series devices.
ALTLVDS_RX Only
Dynamic phase alignment (DPA) mode
support
All Arria and Stratix (1) devices.
DPA PLL calibration support All Stratix (1) series devices.
(1) DPA is available starting from Stratix GX onwards. The first generation Stratix device family does not
support DPA.
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