Xcvr_rx_dc_gain, Xcvr_rx_linear_equalizer_control – Altera Transceiver PHY IP Core User Manual
Page 623
you cannot assign a value for any settings that this parameter controls. For example, for PCIe, the
XCVR_ANALOG_SETTINGS_PROTOCOL
assigns a value to
XCVR_RX_BYPASS_EQ_STAGES_234
. If you also
assign a value to this parameter, a Quartus II Fitter error results as shown in the following example:
Example 19-3: Error (21215)
Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value
on instance "pci_interface_ddf2:u_pci_interface_2|
PCIE_8x8Gb_HARDIP_2:PCIe2_Interface.U_PCIE_CORE|
altpcie_sv_hip_ast_hwtcl:pcie_8x8gb_hardip_2_inst|
altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b
|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:
inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_rx_pma:rx_pma.
sv_rx_pma_inst|rx_pmas[8].rx_pma.rx_pma_buf": Only one QSF
setting for the parameter is allowed.
Options
The following protocol values are defined:
• BASIC
• CPRI
• PCIE_GEN1
• PCIE_GEN2
• SRIO
• XAUI
Assign To
Pin - TX and RX serial data
XCVR_RX_DC_GAIN
Pin Planner and Assignment Editor Name
Receiver Buffer DC Gain Control
Description
Controls the amount of a stage receive-buffer DC gain.
Options
0 –1
Assign To
Pin - RX serial data
XCVR_RX_LINEAR_EQUALIZER_CONTROL
Pin Planner and Assignment Editor Name
Receiver Linear Equalizer Control
UG-01080
2015.01.19
XCVR_RX_DC_GAIN
19-29
Analog Parameters Set Using QSF Assignments
Altera Corporation