Altera Transceiver PHY IP Core User Manual
Page 700
Date
Document
Version
Changes Made
December 2010
1.1
• • Added Stratix V support
• Changed
phy_mgmt_address
from 16 to 9 bits.
• Renamed management interface, adding
phy_ prefix
• Renamed
block_lock
and
hi_ber
signals
rx_block_lock
and
rx_hi_ber
, respectively.
• Added top-level signals for external PMA and reconfigura‐
tion controller in Stratix IV devices. Refer to External PMA
and Reconfiguration Signals.
• Removed the
mgmt_burstcount
signal.
• Changed register map to show word addresses instead of a
byte offset from a base address.
XAUI PHY Transceiver
December 2010
1.1
• Added support for Arria II GX and Cyclone IV GX with hard
PCS
• Renamed management interface, adding
phy_
prefix
• Changed
phy_mgmt_address
from 16 to 9 bits.
• Renamed many signals. Refer to XAUI Top-Level Signals—Soft
PCS and PMA and “XAUI Top-Level Signals–Hard IP PCS and
PMA” as appropriate.
• Changed register map to show word addresses instead of a byte
offset from a base address.
• Removed the
rx_ctrldetect
and
rx_freqlocked
signals.
Interlaken PHY Transceiver
December 2010
1.1
• Added simulation support in ModelSim SE, Synopsys VCS MX,
Cadence NCSim
• Changed number of lanes supported from 4–24 to 1–24.
• Changed reference clock to be 1/20th rather than 1/10th the lane
rate.
• Renamed management interface, adding phy_ prefix
• Changed phy_mgmt_address from 16 to 9 bits.
• Changed many signal names, refer to Top-Level Interlaken PHY
Signals.Changed register map to show word addresses instead of
a byte offset from a base address.
PCI Express PHY (PIPE)
21-40
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core