Altera Transceiver PHY IP Core User Manual
Page 233
Table 9-12: Avalon-ST TX Interface Signals
Signal Name
Direction
Description
tx_parallel_data[(
43:0]
Input
This is TX parallel data driven from the MAC. The ready
latency on this interface is 0, so that the PHY must be able
to accept data as soon as it comes out of reset.
The bits of each 11-bit word have the following definitions
when you enable 8B/10B encoding:
•
tx_parallel_data[7:0]
: TX data bus.
•
tx_parallel_data[8]
: TX data control character.
•
tx_parallel_data[9]
: Force disparity. For the Gen1
and Gen2 PCIe PIPE interface, this signal forces
running disparity to negative in compliance mode.
•
tx_parallel_data[10]
: Disparity field.
• 1'b0: Transmit positive disparity.
• 1'b1: Transmit negative disparity.
• For Gen1 and Gen2 PCIe PIPE - Forces the TX
ouptu to electrical idle.
If 8B/10B encoding is disabled, the width of this interface is
width you specified for FPGA fabric transceiver interface
width If 8B/10B encoding is disabled, when you have
enabled dynamic reconfiguration, the following mapping
applies to each word:
•
tx_parallel_data[7:0]
: Data input bus.
•
tx_parallel_data[10:8]
: Unused.
Refer to
for the location of valid data for a
single- and double-word data buses, with and without the
byte serializer.
tx_clkout
Output
This is the clock for TX parallel data, control, and status
signals.
tx_datak[< n >()-
1:0]
Input
Data and control indicator for the transmitted data. When
0, indicates that tx_data is data, when 1, indicates that tx_
data is control.
tx_forcedisp[< n >(
)-1:0]
Input
When asserted, this control signal enables disparity to be
forced on the TX channel. This signal is created if you turn
On the Enable manual disparity control option on the
8B/10B tab.
tx_dispval[< n >(
)-1:0]
Input
This control signal specifies the disparity of the data. This
port is created if you turn On the Enable disparity control
option on the 8B/10B tab.
9-20
Data Interfaces
UG-01080
2015.01.19
Altera Corporation
Custom PHY IP Core