Speed detection parameters, Speed detection parameters -5 – Altera Transceiver PHY IP Core User Manual
Page 114
Parameter Name
Options
Description
Enable IEEE 1588 Precision Time
Protocol
On/Off
When you turn this option On, the core includes
a module in the PCS to implement the IEEE
1588 Precision Time Protocol.
PHY ID (32 bit)
32-bit value
An optional 32-bit value that serves as a unique
identifier for a particular type of PCS. The
identifier includes the following components:
• Bits 3-24 of the Organizationally Unique
Identifier (OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value which
is 0x00000000.
PHY Core version (16 bits)
16-bit value
This is an optional 16-bit value identifies the
PHY core version.
Reference clock frequency
125.00 MHz
62.50 MHz
Specifies the clock frequency for the
1GBASE-KR PHY IP Core. The default is 125
MHz.
Related Information
on page 3-30
Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/
10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential
Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GE and 10GE
modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
Table 5-5: Speed Detection
Parameter Name
Options
Description
Enable automatic speed detection On
Off
When you turn this option On, the core includes
the Sequencer block that sends reconfiguration
requests to detect 1G or 10GbE when the Auto
Negotiation block is not able detect AN data.
Avalon-MM clock frequency
100-125 MHz
Specifies the clock frequency for
phy_mgmt_clk
.
UG-01080
2015.01.19
Speed Detection Parameters
5-5
1G/10 Gbps Ethernet PHY IP Core
Altera Corporation