Xaui phy pma channel controller interface, Xaui phy pma channel controller interface -15 – Altera Transceiver PHY IP Core User Manual
Page 155
Signal Name
Direction
Description
xgmii_tx_clk
Input
The XGMII TX clock which runs at 156.25 MHz.
Connect xgmii_tx_clk to xgmii_rx_clk to guarantee this
clock is within 150 ppm of the transceiver reference
clock.
xgmii_rx_clk
Output
This clock is generated by the same reference clock that
is used to generate the transceiver clock. Its frequency is
156.25 MHz. Use this clock for the MAC interface to
minimize the size of the FIFO between the MAX and
SDR XGMII RX interface.
Refer to Transceiver Reconfiguration Controller for additional information about reset.
Related Information
Transceiver Reconfiguration Controller IP Core Overview
XAUI PHY PMA Channel Controller Interface
This sectiondescribes the signals in the PMA channel controller interface.
Table 6-11: PMA Channel Controller Signals
Signal Name
Direction
Description
cal_blk_powerdown
Input
Powers down the calibration block. A high-to-low
transition on this signal restarts calibration. Only available
in Arria II GX, HardCopy IV, and Stratix IV GX, and
Stratix IV GT devices.
gxb_powerdown
Input
When asserted, powers down the entire transceiver block.
Only available in Arria II GX, HardCopy IV, and Stratix
IV GX, and Stratix IV GT devices.
pll_powerdown
Input
Powers down the CMU PLL. Only available in Arria II
GX, HardCopy IV, and Stratix IV GX, and Stratix IV GT
devices.
pll_locked
Output
Indicates CMU PLL is locked. Only available in Arria II
GX, HardCopy IV, and Stratix IV GX, and Stratix IV GT
devices.
rx_recovered_clk[3:0]
Output
This is the RX clock which is recovered from the received
data stream.
rx_ready
Output
Indicates PMA RX has exited the reset state and the
transceiver can receive data.
tx_ready
Output
Indicates PMA TX has exited the reset state and the
transceiver can transmit data.
UG-01080
2015.01.19
XAUI PHY PMA Channel Controller Interface
6-15
XAUI PHY IP Core
Altera Corporation