Altera Transceiver PHY IP Core - Manual (Page 391)

Table 13-15: Rate Match FIFO Parameters
Parameter Range Description
Enable RX rate match
FIFO
On/Off When you turn this option On, the PCS includes a FIFO
to compensate for the very small frequency differences
between the local system clock and the RX recovered
clock.
RX rate match insert/
delete +ve pattern (hex)
User-specified 20
bit pattern
Specifies the +ve (positive) disparity value for the RX rate
match FIFO as a hexadecimal string.
RX rate match insert/
delete -ve pattern (hex)
User-specified 20
bit pattern
Specifies the -ve (negative) disparity value for the RX rate
match FIFO as a hexadecimal string.
When you enable the simplified data interface and enable the rate match FIFO status ports, the rate match
FIFO bits map to the high-order bits of the data bus as listed in the following table. This table uses the
following definitions:
• Basic double width: The Standard PCS protocol mode GUI option is set to basic. The FPGA data
width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
• Serial TM RapidIO double width: You are implementing the Serial RapidIO protocol. The FPGA data
width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
Note: If you have the auto-negotiation state machine in your transceiver design, please note that the rate
match FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets
during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered
sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base
Support Solution .
13-16 Rate Match FIFO
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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