Altera Transceiver PHY IP Core User Manual
Page 668

Chapter
Document
Version
Changes Made
1G/10GbE Ethernet
PHY IP Core
2.6
Made the following changes:
• Corrected an error in the description of
pcs_mode_rc[5:0]
in
Table 5-15: Dynamic Reconfiguration Interface Signals. Added
back the option for GigE data mode and 10G data mode with
FEC.
• Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
• Updated the descriptions of
tm_in_trigger[3:0]
and
tm_out_
trigger [3:0]
signals in Table 5-10: Control and Status Signals.
• Updated the descriptions of
xgmii_tx_clk
and
xgmii_rx_clk
signals in Table 5-7: SGMII and GMII signals.
• Updated the description of
en_lcl_rxeq
and
rxeq_done
signals
in Table 5-15: Dynamic Reconfiguration Interface Signals.
• Updated the description of
tx_clkout_1g
signal in Table 5-6:
Clock and Reset Signals.
• Added a note about performing read-modify-writes for all
registers in 1G/10GbE PHY Register Definitions section.
• Added a clarification about reset sequencer in the 1G/10GbE
PHY Clock and Reset Interfaces section on page 5-7.
• Updated
tx_clkout_1g
,
rx_clkout_1g
,
tx_coreclkin_1g
, and
rx_coreclkin_1g
connections in Figure 5-3: Clocks for Standard
and 10G PCS and TX PLLs.
XAUI
2.6
Added the statement "This register is only available in the hard
XAUI implementation" for 0x82 and 0x83, polarity inversion" for
0x082 and 0x083, polarity inversion registers.
Custom PHY IP Core 2.6
Made the following changes:
• Corrected the description of
tx_datak
signal in Table 9-12:
Avalon -ST TX Interface Signals.
• Corrected the available word alignment pattern lengths for 20 bit
PMA-PCS interface width in manual mode in Table 9-6: More
Information About Word Aligner Functions.
• Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
Low Latency PHY IP
Core
2.6
Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
21-8
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core