Altera Transceiver PHY IP Core User Manual
Page 576
post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer.
The RX data is also available to the FPGA fabric. In the TX channel, only the TX buffer is active.
Figure 16-15: Pre- and Post-CDR Reverse Serial Loopback Paths
In this figure, grayed-out blocks are not active in these modes. The number (2) shows the post-CDR
loopback path and the number (3) shows pre-CDR reverse serial loopback path.
Tx P C S
Rx P C S
Tx PMA
Serializer
Rx PMA
Deserializer
To FPGA fabric
for verification
Transceiver
CDR
(2)
(3)
FPGA
Fabric
In addition to the pre-CDR and post-CDR loopback modes available in the Transceiver Reconfiguration
Controller register map, all the of PHYs, with the exception of PCI Express, support serial loopback mode.
You enable this mode by writing the
phy_serial_loopback
register (0x061) using the Avalon-MM PHY
management interface except for the Native PHY IP. In Native PHY IP, you can enable the serial loopback
mode by driving
rx_seriallpbken
input port to 1'b1. Also, PCI Express supports reverse parallel
loopback mode as required by the PCI Express Base Specification.
The following figure shows the datapath for serial loopback. The data from the FPGA fabric passes
through the TX channel and is looped back to the RX channel, bypassing the RX buffer. The received data
is available to the FPGA fabric for verification. Using the serial loopback option, you can check the
operation of all enabled PCS and PMA functional blocks in the TX and RX channels. When serial
loopback is enabled, the TX channel sends the data to both the tx_serial_data output port and the RX
channel.
UG-01080
2015.01.19
Loopback Modes
16-59
Transceiver Reconfiguration Controller IP Core Overview
Altera Corporation