Altera Transceiver PHY IP Core - Manual (Page 581)

Parameterizing the Transceiver PHY Reset Controller IP
This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the IP Catalog. You
can customize the following Transceiver PHY Reset Controller parameters for different modes of
operation by clicking Tools > IP Catalog.
To parameterize and instantiate the Transceiver PHY Reset Controller IP core:
1. For Device Family, select your target device from the list.
2. Click Installed IP > Library > Interface Protocols > Transceiver PHY > Transceiver PHY Reset
Controller.
3. Select the options required for your design. For a description of these options, refer to the Transceiver
PHY Reset Controller Parameters.
4. Click Finish. The wizard generates files representing your parameterized IP variation for synthesis and
simulation.
Transceiver PHY Reset Controller Parameters
The Quartus ® II software provides a GUI to define and instantiate a Transceiver PHY Reset Controller to
reset transceiver PHY and external PLL.
Table 17-3: General Options
Name Range Description
Number of transceiver channels
1-1000
Specifies the number of channels that connect to
the Transceiver PHY Reset Controller IP core.
The upper limit of the range is determined by
your FPGA architecture.
Number of TX PLLs
1-1000
Specifies the number of TX PLLs that connect to
the Transceiver PHY Reset Controller IP core.
Input clock frequency
1-500 MHz
Input clock to the Transceiver PHY Reset
Controller IP core. The frequency of the input
clock in MHz. The upper limit on the input
clock frequency is the frequency achieved in
timing closure.
Synchronize reset input On /Off When On, the Transceiver PHY Reset
Controller synchronizes the reset to the
Transceiver PHY Reset Controller input clock
before driving it to the internal reset logic.
When Off, the reset input is not synchronized.
Use fast reset for simulation On /Off When On, the Transceiver PHY Reset
Controller uses reduced reset counters for
simulation.
Separate interface per channel/
PLL
On /Off When On, the Transceiver PHY Reset
Controller provides a separate reset interface for
each channel and PLL.
TX PLL
17-4 Parameterizing the Transceiver PHY Reset Controller IP
UG-01080
2015.01.19
Altera Corporation Transceiver PHY Reset Controller IP Core
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