Altera Transceiver PHY IP Core - Manual (Page 535)

Note: All undefined register bits are reserved.
Table 16-12: EyeQ Offsets and Values
Note: The default value for all the register bits mentioned in this table is 0.
Offset Bits R/W Register Name Description
0x0
[4:3] RW
BERB Snap Shot and
Reset
Only available when you turn on the Enable Bit
Error Rate Block in the Transceiver Reconfigura‐
tion Controller IP Core GUI. The following
encodings are defined:
• 2'b00: Reserved.
• 2'b01: Reset everything, snapshot and counters
are reset to 0.
• 2'b10: Take a snapshot. Copy the counter
values into local registers for read access. These
values are not updated until another snapshot
is taken.
• 2'b11: Snapshot and reset. Take a snapshot of
the counter values. Reset the counters and
leave the snap shot untouched.
[2] RW
Counter Enable
Only available when you turn on the Enable Bit
Error Rate Block in the Transceiver Reconfigura‐
tion Controller IP Core GUI.
When set to 1, the counters accumulate bits and
errors. When set to 0, pauses accumulation,
preserving the current values.
[1] RW
BERB Enable
Only available when you turn on the Enable Bit
Error Rate Block in the Transceiver Reconfigura‐
tion Controller IP Core GUI.
When set to 1, enables the BER. When set to 0,
disables the BER counters and the bit checker.
[0] RW
Enable Eye Monitor
Writing a 1 to this bit enables the Eye monitor.
0x1 [5:0] RW
Horizontal phase
Taken together, the
Horizontal phase
and
vertical height
specify the Cartesian x-y
coordinates of the sample point on the eye
diagram. You can increment through 64 phases
over 2 UI on the horizontal axis.
0x2 [5:0] RW
Vertical height
Taken together, the
horizontal phase
and
vertical height
specify the Cartesian x-y
coordinates of the sample point on the eye
diagram. You can specify 64 heights on the
vertical axis.
16-18 Transceiver Reconfiguration Controller EyeQ Registers
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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