Xaui phy optional pma control and status interface – Altera Transceiver PHY IP Core User Manual
Page 156
XAUI PHY Optional PMA Control and Status Interface
You can access the state of the optional PMA control and status signals available in the soft IP implemen‐
tation using the Avalon-MM PHY Management interface to read the control and status registers which
are detailed in XAUI PHY IP Core Registers . However, in some cases, you may need to know the
instantaneous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can
include the required signal in the top-level module of your XAUI PHY IP Core.
Table 6-12: Optional Control and Status Signals—Soft IP Implementation
Signal Name
Direction
Description
rx_channelaligned
Output
When asserted, indicates that all 4 RX channels
are aligned.
rx_disperr[7:0]
Output
Received 10-bit code or data group has a
disparity error. It is paired with
rx_errdetect
which is also asserted when a disparity error
occurs. The
rx_disperr
signal is 2 bits wide
per channel for a total of 8 bits per XAUI link.
rx_errdetect[7:0]
Output
When asserted, indicates an 8B/10B code
group violation. It is asserted if the received 10-
bit code group has a code violation or disparity
error. It is used along with the
rx_disperr
signal to differentiate between a code violation
error, a disparity error, or both. The
rx_
errdetect
signal is 2 bits wide per channel for
a total of 8 bits per XAUI link.
rx_syncstatus[7:0]
Output
Synchronization indication. RX synchroniza‐
tion is indicated on the
rx_syncstatus
port of
each channel. The
rx_syncstatus
signal is 2
bits per channel for a total of 8 bits per hard
XAUI link. The
rx_syncstatus
signal is 1 bit
per channel for a total of 4 bits per soft XAUI
link.
rx_is_lockedtodata[3:0]
Output
When asserted indicates that the RX CDR PLL
is locked to the incoming data.
rx_is_lockedtoref[3:0]
Output
When asserted indicates that the RX CDR PLL
is locked to the reference clock.
tx_clk312_5
Output
This is the clock used for the SDR XGMII
interface.
You can access the state of the PMA control and status signals available in the hard IP implementation
using the Avalon-MM PHY Management interface to read the control and status registers which are
detailed in XAUI PHY IP Core Registers. However, in some cases, you may need to know the instanta‐
6-16
XAUI PHY Optional PMA Control and Status Interface
UG-01080
2015.01.19
Altera Corporation
XAUI PHY IP Core