Altera Transceiver PHY IP Core - Manual (Page 641)

• SDLV_25MV=2
• SDLV_20MV=1
• SDLV_15MV=0
For the PCIe PIPE PHY, SATA, and SAS.
The signal detect output is high when the receiver peak-to-peak differential voltage (diff p-p) > V
th
x 4.
For example, a setting of 6 translates to peak-to-peak differential voltage of 180mV (4*45mV). The V
diff p-
p
must be > 180mV to turn on the signal detect circuit.
Options
• 0-7
Assign To
Pin - RX serial data
XCVR_TX_COMMON_MODE_VOLTAGE
Pin Planner and Assignment Editor Name
Transmitter Common Mode Driver Voltage
Description
Transmitter common-mode driver voltage.
Note: Contact Altera for using this assignment.
Related Information
How to Contact Altera on page 21-42
XCVR_TX_PRE_EMP_PRE_TAP_USER
Pin Planner and Assignment Editor Name
Transmitter Pre-emphasis Pre-Tap user
Description
Specifies the TX pre-emphasis pretap setting value, including inversion.
Note: This parameter must be set in conjunction with
XCVR_TX_VOD
,
XCVR_TX_PRE_EMP_1ST_POST_TAP
,
and
XCVR_TX_PRE_EMP_2ND_POST_TAP
. All combinations of these settings are not legal. Refer to the
Stratix V Device Datasheet for more information.
Options
0–31
Assign To
Pin - TX serial data
UG-01080
2015.01.19
XCVR_TX_COMMON_MODE_VOLTAGE 19-47
Analog Parameters Set Using QSF Assignments Altera Corporation
Send Feedback