Altera Transceiver PHY IP Core - Manual (Page 394)

Table 13-17: Word Aligner and BitSlip Parameters
Parameter Range Description
Enable TX bit slip On/Off When you turn this option On, the PCS
includes the bitslip function. The outgoing TX
data can be slipped by the number of bits
specified by the
tx_bitslipboundarysel
control signal.
Enable tx_std_bitslipboundarysel
control input port.
On/Off When you turn this option On, the PCS
includes the optional
tx_std_bitslipboun-
darysel
control input port.
RX word aligner mode bit_slip
sync_sm
manual Specifies one of the following 3 modes for the
word aligner:
• Bit_slip: You can use bit slip mode to shift
the word boundary. For every rising edge of
the
rx_bitslip
signal, the word boundary is
shifted by 1 bit. Each bitslip removes the
earliest received bit from the received data.
• Sync_sm: In synchronous state machine
mode, a programmable state machine
controls word alignment. You can only use
this mode with 8B/10B encoding. The data
width at the word aligner can be 10 or 20
bits. When you select this word aligner
mode, the synchronous state machine has
hysteresis that is compatible with XAUI.
However, when you select cpri for the
Standard PCS Protocol Mode, this option
selects the deterministic latency word aligner
mode.
• Manual: This mode enables word alignment
by asserting the
rx_std_wa_pattern
. This is
an edge sensitive signal.
RX word aligner pattern length 7,8,10,16,20, 32,40 Specifies the length of the pattern the word
aligner uses for alignment. The pattern is
specified in LSBtoMSB order.
RX word aligner pattern (hex) User-specified Specifies the word aligner pattern in hex.
Number of word alignment
patterns to achieve sync
1–256
Specifies the number of valid word alignment
patterns that must be received before the word
aligner achieves synchronization lock. The
default is 3.
UG-01080
2015.01.19
Word Aligner and BitSlip Parameters 13-19
Arria V Transceiver Native PHY IP Core Altera Corporation
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